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1 for more information www.linear.com/ltc7801 typical a pplica t ion fea t ures descrip t ion 150v low i q , synchronous step-down dc/dc controller the lt c ? 7801 is a high performance step-down switching regulator dc/dc controller that drives an all n-channel synchronous power mosfet stage that can operate from input voltages up to 140v. a constant frequency current mode architecture allows a phase-lockable frequency of up to 850khz. the gate drive voltage can be programmed from 5v to 10v to allow the use of logic or standard-level fets to maxi - mize efficiency. an integrated switch in the top gate driver eliminates the need for an external bootstrap diode. an internal charge pump allows for 100% duty cycle operation. the low 40a no-load quiescent current extends operating run time in battery-powered systems. opti-loop ? com- pensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the lt c7801 features a precision 0.8v reference and power good output indicator. the output voltage can be programmed between 0.8v to 60v using external resistors. high efficiency high voltage 12v output step-down regulator efficiency and power loss vs load current a pplica t ions n wide v in range: 4v to 140v (150v abs max) n wide output voltage range: 0.8v to 60v n adjustable gate drive level : 5v to 10v (opti-drive) n low operating i q : 40a (shutdown = 10a) n 100% duty cycle operation n no external bootstrap diode required n selectable gate drive uvlo thresholds n onboard ldo or external nmos ldo for drv cc n extv cc ldo powers drivers from v out n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n selectable continuous, pulse-skipping or low ripple burst mode ? operation at light loads n adjustable burst clamp n power good output voltage monitor n programmable input overvoltage lockout n small 24-lead 4mm 5mm qfn or tssop packages n automotive and industrial power systems n high voltage battery operated systems n telecommunications power systems l , lt, ltc, ltm, burst mode, opti-loop, polyphase, linear technology and the linear logo are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258. *v out follows v in when v in < 12v lt c7801 7801f 0.1f 0.1f 10k 4.7nf 100pf 100f 33h 30.1k v in intv cc 0.1f cpump_en ith ss freq gnd ltc7801 tg sw bg sense+ 4.7f sense? extv cc v fb boost run ndrv drv cc v in 7v to 140v v out 7801 ta01a 12v* 5a x3 power loss v in = 48v efficiency v in 6m = 24v load current (a) 0.0001 0.001 0.01 0.1 1 10 0 10 511k 20 30 40 50 60 70 80 90 100 1 150f 10 100 1k 10k efficiency (%) power loss (mw) 7801 ta01b 36.5k 1nf
2 for more information www.linear.com/ltc7801 p in c on f igura t ion a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ....................... C 0.3 v to 150v top side driver voltage boost ............... C 0. 3v to 150v switch voltage (sw) ................................... C 5v to 150v drv cc , (boost-sw) voltages .................... C 0.3 v to 11v bg, tg ............................................................... ( note 8) run voltage ............................................. C 0.3v to 150v sense + , sense C voltages ......................... C 0. 3v to 65v pllin, pgood voltages .............................. C 0. 3v to 6v mode, drvuv voltages .............................. C 0. 3v to 6v freq voltage ............................................... C 0.3 v to 6v (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 top view fe package 24-lead plastic tssop 24 23 22 21 20 19 18 17 16 15 14 13 sense ? ss v fb ith mode gnd crump_en pllin pgood freq drvset drvuv sense + ovlo intv cc run extv cc v in ndrv drv cc bg boost sw tg 25 t jmax = 150c, ja = 33c/w exposed pad (pin 25) is gnd, must be soldered to pcb for ra ted electrical and thermal characteristics 8 9 top view ufd package 24-lead (4mm 5mm) plastic qfn 25 10 11 12 24 23 22 21 20 6 5 4 3 2 1 v fb ith mode gnd cpump_en pllin pgood run extv cc v in ndrv drv cc bg boost ss sense ? sense + ovlo intv cc freq drvset drvuv tg sw 7 14 15 16 17 18 19 13 t jmax = 150c, ja = 43c/w exposed pad (pin 25) is gnd, must be soldered to pcb for ra ted electrical and thermal characteristics o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc7801efe#pbf ltc7801efe#trpbf ltc7801fe 24-lead plastic tssop C40c to 125c ltc7801ife#pbf ltc7801ife#trpbf ltc7801fe 24-lead plastic tssop C40c to 125c ltc7801hfe#pbf ltc7801hfe#trpbf ltc7801fe 24-lead plastic tssop C40c to 150c ltc7801eufd#pbf ltc7801eufd#trpbf 7801 24-lead (4mm 5mm) plastic qfn C40c to 125c ltc7801iufd#pbf ltc7801iufd#trpbf 7801 24-lead (4mm 5mm) plastic qfn C40c to 125c ltc7801hufd#pbf ltc7801hufd#trpbf 7801 24-lead (4mm 5mm) plastic qfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http://www.linear.com/product/ltc7801#orderinfo drvset, cp ump_ en voltages ..................... C 0. 3v to 6v ndrv ................................................................. ( note 9) extv cc voltage ......................................... C 0. 3v to 14v ith, v fb voltages ......................................... C 0. 3v to 6v ss, ovlo voltages ...................................... C 0. 3v to 6v operating junction temperature range (notes 2, 3) lt c78 01 e, lt c7801 i .......................... C 40 c to 125 c lt c78 01 h .......................................... C 40 c to 150 c storage temperature range .................. C 65 c to 150 c lt c7801 7801f
3 for more information www.linear.com/ltc7801 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in input supply operating voltage range (note 10) drvuv = 0v l 4 140 v v out regulated output voltage set point 0.8 60 v v fb regulated feedback voltage (note 4); ith voltage = 1.2v 0c to 85c l 0.792 0.788 0.800 0.800 0.808 0.812 v v i fb feedback current (note 4) C0.006 0.050 a reference voltage line regulation (note 4) v in = 4.5v to 150v 0.002 0.02 %/v output voltage load regulation (note 4) measured in servo loop, ?ith voltage = 1.2v to 0.7v l 0.01 0.1 % (note 4) measured in ser vo loop, ?ith v oltage = 1.2v to 1.6v l C0.01 C0.1 % g m transconductance amplifier gm (note 4) ith = 1.2v, sink/source 5a 2 mmho i q input dc supply current (note 5) v drvset = 0v pulse skip or forced continuous mode v fb = 0.83v (no load) 2.5 ma sleep mode v fb = 0.83v (no load) 40 55 a shutdown run = 0v 10 20 a uvlo undervoltage lockout drv cc ramping up drvuv = 0v drvuv = int v cc , drvset = intv cc l l 4.0 7.5 4.2 7.8 v v d rv cc ramping down drvuv = 0v drvuv = int v cc , drvset = intv cc l l 3.6 6.4 3.8 6.7 4.0 7.0 v v v run on run pin on threshold v run rising l 1.1 1.2 1.3 v v run hyst run pin hysteresis 80 mv ovlo overvoltage lockout threshold v ovlo rising l 1.1 1.2 1.3 v ovlo hyst ovlo hysteresis 100 mv ovlo delay 1 s feedback overvoltage protection measured at v fb , relative to regulated v fb 7 10 13 % i sense + sense + pin current 1 a i sense C sense C pin current sense C < v intvcc C 0.5v sense C > v intvcc + 0.5v 850 1 a a maximum duty factor in dropout cpump_en = 0v, freq = 0v cpump_en = intv cc 98 100 99 % i ss soft-start charge current v ss = 0v 8 10 12 a v sense(max) maximum current sense threshold v fb = 0.7v, v sense C = 3.3v l 66 75 84 mv the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2), v in = 12v, v run = 5v, v extvcc = 0v, v drvset = 0v unless otherwise noted. lt c7801 7801f
4 for more information www.linear.com/ltc7801 symbol parameter conditions min typ max units gate driver tg pull-up on-resistance tg pull-down on-resistance v drvset = intv cc 2.2 1.0 bg pull-up on-resistance bg pull-down on-resistance v drvset = intv cc 2.0 1.0 boost to dr v cc switch on-resistance v sw = 0v, v drvset = intv cc 11 tg transition time: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns bg transition t ime: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns top gate off to bottom gate on delay synchronous switch-on delay t ime c load = 3300pf each driver, v drvset = intv cc 55 ns bottom gate off to t op gate on delay t op switch-on delay time c load = 3300pf each driver, v drvset = intv cc 50 ns t on(min) tg minimum on-time (note 7) v drvset = intv cc 80 ns charge pump for high side driver supply i cpump charge pump output current v boost =16v, v sw = 12v, v freq = 0v v boost =19v, v sw = 12v, v freq = 0v 65 55 a a drv cc ldo regulator drv cc voltage from ndrv ldo regulator ndrv driving external nfet, v extvcc = 0v 7v < v in < 150v, drvset = 0v 11v < v in < 150v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v d rv cc load regulation from ndrv ldo regulator ndrv driving external nfet i cc = 0ma to 50ma, v extvcc = 0v 0 1.0 % drv cc voltage from internal v in ldo ndrv = drv cc , v extvcc = 0v 7v < v in < 150v, drvset = 0v 11v < v in < 150v, drvset = intv cc 5.6 9.5 5.85 9.85 6.1 10.3 v v d rv cc load regulation from v in ldo i cc = 0ma to 50ma, v extvcc = 0v drvset = 0v drvset = intv cc 1.4 0.9 2.5 2.0 % % d rv cc voltage from internal extv cc ldo 7v < v extvcc < 13v, drvset = 0v 11v < v extvcc < 13v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v d rv cc load regulation from internal extv cc ldo i cc = 0ma to 50ma drvset = 0v, v extvcc = 8.5v drvset = intv cc , v extvcc = 13v 0.7 0.5 2.0 2.0 % % extv cc ldo switchover voltage extv cc ramping positive drvuv = 0v drvuv = intv cc , drvset = intv cc 4.5 7.4 4.7 7.7 4.9 8.0 v v ext v cc hysteresis 250 mv programmable drv cc r drvset = 50k ndrv driving external nfet, v extvcc = 0v 5.0 v programmable drv cc r drvset = 70k ndrv driving external nfet, v extvcc = 0v 6.4 7.0 7.6 v programmable drv cc r drvset = 90k ndrv driving external nfet, v extvcc = 0v 9.0 v e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2), v in = 12v, v run = 5v, v extvcc = 0v, v drvset = 0v unless otherwise noted. lt c7801 7801f
5 for more information www.linear.com/ltc7801 symbol parameter conditions min typ max units intv cc ldo regulator v intvcc intv cc voltage i cc = 0ma to 2ma 4.7 5.0 5.2 v oscillator and phase-locked loop programmable frequency r freq = 25k, pllin = dc voltage 105 khz programmable frequency r freq = 65k, pllin = dc voltage 375 440 505 khz programmable frequency r freq =105k, pllin = dc voltage 835 khz low fixed frequency v freq = 0v, pllin = dc voltage 320 350 380 khz high fixed frequency v freq = intv cc , pllin = dc voltage 485 535 585 khz f sync synchronizable frequency pllin = external clock l 75 850 khz pllin input high level pllin input low level pllin = external clock pllin = external clock l l 2.8 0.5 v v pgood output v pgl pgood voltage low i pgood = 2ma 0.02 0.04 v i pgood pgood leakage current v pgood = 3.3v 10 a pgood trip level v fb with respect to set regulated voltage v fb ramping negative hysteresis C13 C10 2.5 C7 % % v fb with respect to set regulated voltage v fb ramping positive hysteresis 7 10 2.5 13 % % delay for reporting a fault 40 s e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2), v in = 12v, v run = 5v, v extvcc = 0v, v drvset = 0v unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum ratings for extended periods may affect device reliability and lifetime. note 2: the ltc7801 is tested under pulsed load conditions such that t j t a . the ltc7801e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc7801i is guaranteed over the C40c to 125c operating junction temperature range and the ltc7801h is guaranteed over the C40c to 150c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. high temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125oc. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja = 33c/w for the tssop package and ja = 43c/w for the qfn package. note 3 : this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc7801 is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v fb . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the ltc7801e and ltc7801i, 150c for the ltc7801h). for the ltc7801i and ltc7801h, the specification at 0c is not tested in production and is assured by design, characterization and correlation to production testing at C40c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see the applications information section. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current >40% of i max (see minimum on-time considerations in the applications information section). note 8: do not apply a voltage or current source to these pins. they must be connected to capacitive loads only, otherwise permanent damage may occur. note 9: do not apply a voltage or current source to the ndrv pin, other than tying ndrv to drv cc when not used. if used it must be connected to capacitive loads only (see drv cc regulators in the applications information section), otherwise permanent damage may occur. note 10: the minimum input supply operating range is dependent on the drv cc uvlo thresholds as determined by the drvuv pin setting. lt c7801 7801f
6 for more information www.linear.com/ltc7801 typical p er f or m ance c harac t eris t ics load step burst mode operation load step pulse-skipping mode load step forced continuous mode inductor current at light load soft start-up regulated feedback voltage vs temperature efficiency and power loss vs load current efficiency vs load current efficiency vs input voltage 200s/div v out 100mv/div ac coupled i l 1a/div 7801 g04 v in = 24v figure 13 circuit 200s/div v out 100mv/div ac coupled i l 1a/div 7801 g04 v in = 24v figure 13 circuit 200s/div v out 100mv/div ac coupled i l 1a/div 7801 g06 v in = 24v figure 13 circuit 200s/div forced continuous mode burst mode operation 2a/div pulse skipping mode 7801 g07 v in = 24v figure 13 circuit 2ms/div v out 2v/div run 2v/div 7801 g08 v in = 24v figure 13 circuit lt c7801 7801f fcm efficiency ?75 ?50 ?25 0 25 50 75 100 125 150 figure 13 circuit 792 794 796 798 800 802 804 806 808 regulated feedback voltage (v) burst loss 7801 g09 load current (a) 0.0001 0.001 0.01 0.1 1 10 burst efficiency 0 10 20 30 40 50 60 70 80 90 v in = 24v 100 1 10 100 1k 10k efficiency (%) power loss (mw) 7801 g01 v v out = 12v out = 12v v in = 24v v in = 48v v in pulse?skipping = 100v v in = 140v load current (a) 0.0001 0.001 0.01 0.1 1 loss 10 0 10 20 30 40 50 60 70 80 pulse?skipping 90 100 efficiency (%) 7801 g02 figure 13 circuit v out = 12v i load = 4a input voltage (v) 20 40 efficiency 60 80 100 120 140 80 82 84 86 88 fcm loss 90 92 94 96 98 100 efficiency (%) 7801 g03 figure 13 circuit temperature (c)
7 for more information www.linear.com/ltc7801 typical p er f or m ance c harac t eris t ics sense C pin input current vs v sense voltage sense C pin input bias current vs temperature undervoltage lockout threshold vs temperature foldback current limit maximum current sense threshold vs ith voltage run/ovlo threshold vs temperature drv cc and extv cc vs load current extv cc switchover and drv cc voltages vs temperature extv cc switchover and drv cc voltages vs temperature lt c7801 7801f 0 500 600 700 800 900 1000 sense ? current (a) 7801 g13 v out intv cc + 0.5v v out intv cc ? 0.5v 20 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 40 150 0 100 200 300 400 500 600 700 800 60 900 1000 sense ? current (a) 7801 g14 rising rising falling falling drvuv = intv cc drvuv = 0v 80 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 100 150 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 4.0 7.5 8.0 drv cc voltage (v) 7801 g15 ovlo rising run rising run falling ovlo falling temperature (c) ?75 4.5 ?50 ?25 0 25 50 75 100 125 150 1.00 5.0 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 run/ovlo pin voltage (v) 7801 g18 5.5 feedback voltage (mv) 0 100 200 300 400 500 600 700 800 extv cc = 5v 6.0 0 10 20 30 40 50 60 70 80 90 6.5 100 maximum current sense voltage (mv) 7801 g16 5% duty cycle pulse?skipping burst mode operation forced continuous v ith drv cc voltage (v) (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 7801 g10 ?20 0 20 40 60 80 100 current sense voltage (mv) 7801 g17 drvuv = drvset = 0v extv cc rising extv cc falling extv cc = 8.5v ndrv ldo (ndrv fet), extv cc = 0v v in ldo (no ndrv fet), v in ldo (no ndrv fet), extv cc = 0v, temperature (c) ?75 ?50 ?25 0 25 50 75 extv cc = 0v 100 125 150 4.0 4.5 5.0 5.5 6.0 6.5 drv cc voltage (v) ndrv ldo (ndrv fet), 7801 g11 drvuv = drvset = intv cc extv cc rising extv cc falling extv cc = 8.5v ndrv ldo (ndrv nfet), extv cc = 0v v in ldo (no ndrv nfet), extv cc = 0v temperature (c) extvcc = 0v ?75 ?50 ?25 0 25 50 75 100 125 150 extv cc = 8.5v 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 drv cc voltage (v) 7801 g12 drvuv = drvset = 0v v sense common mode voltage (v) 0 5 10 15 20 25 30 35 40 load current (ma) 45 50 55 60 65 0 100 200 300 400
8 for more information www.linear.com/ltc7801 typical p er f or m ance c harac t eris t ics quiescent current vs temperature oscillator frequency vs temperature ss pull-up current vs temperature boost charge pump voltage vs sw voltage boost charge pump charging current vs frequency boost charge pump charging current vs sw voltage drv cc line regulation shutdown current vs temperature shutdown current vs input voltage lt c7801 7801f 30 90 100 quiescent current (a) 7801 g22 freq = 0v freq = intv cc temperature (c) ?75 ?50 ?25 45 0 25 50 75 100 125 150 300 350 400 60 450 500 550 600 frequency (khz) 7801 g23 temperature (c) ?75 ?50 ?25 75 0 25 50 75 100 125 150 8.0 8.5 9.0 90 9.5 10.0 10.5 11.0 11.5 12.0 ss current (a) 7801 g24 freq = 350khz 10m between boost and sw 105 150c 25c ?55c sw voltage (v) 0 5 10 15 20 25 120 30 35 40 45 50 55 60 65 0 1 135 2 3 4 5 6 7 8 9 10 (boost - sw) voltage (v) 150 7801 g25 v boost = 16v v sw = 12v 150c 25c ?55c operating frequency (khz) 0 100 200 5 300 400 500 600 700 800 900 1000 0 10 drvset = intv cc 6 20 30 40 50 60 70 80 90 100 charge pump charging current (a) 7 7801 g26 freq = 350khz v boost - v sw = 7v 150c 25c ?55c sw voltage (v) 0 5 10 8 15 20 25 30 35 40 45 50 55 60 9 65 0 10 20 30 40 50 60 70 80 10 90 100 charge pump charging current (a) 7801 g27 v boost - v sw = 4v 11 drv cc voltage (v) 7801 g19 v in = 12v temperature (c) drvset = 0v ?75 ?50 ?25 0 25 50 75 100 125 150 no ndrv fet 0 2 4 6 8 10 12 14 16 18 extv cc = 0v 20 shutdown current (a) 7801 g20 v in = 6.3v input voltage (v) 0 15 30 45 60 ndrv fet 75 90 105 120 135 150 0 5 10 15 input voltage (v) 20 25 30 shutdown current (a) 7801 g21 v in = 12v burst mode operation drvset = 70k drvset = 0v drvset = intv cc 0 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 15 150 0 10 20 30 40 50 60 70 80
9 for more information www.linear.com/ltc7801 v fb (pin 1/pin 3) : feedback input. this pin receives the remotely sensed feedback voltage from an external resistor divider across the output. ith (pin 2/pin 4): error amplifier output and switching regulator compensation point. the current comparator trip point increases with this control voltage. mode (pin 3/pin 5): mode select and burst clamp adjust input. this input determines how the ltc7801 operates at light loads. pulling this pin to ground selects burst mode operation with the burst clamp level defaulting to 25% of v sense(max) . tying this pin to a voltage between 0.5v and 1.0v selects burst mode operation and adjusts the burst clamp between 10% and 60%. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.4v and less than intv cc C 1.3v selects pulse-skipping operation. gnd (pin 4, exposed pin 25/pin 6, exposed pad pin 25): ground. all gnd pins must be tied together for operation. the exposed pad must be soldered to pcb ground for rated electrical and thermal performance. cpump_en (pin 5/pin 7): charge pump enable pin for the top gate driver boost supply. tying this pin to intv cc enables the boost supply charge pump and allows for 100% duty cycle operation in dropout. tying this pin to gnd disables the charge pump and enables boost refresh, allowing for 99% duty cycle operation in dropout. do not float this pin. pllin (pin 6/ pin 8): external synchronization input to phase detector. when an external clock is applied to this pin, the phase-locked loop will force the rising tg signal to be synchronized with the rising edge of the external clock. if the mode pin is set to forced continuous mode or burst mode operation, then the regulator operates in forced continuous mode when synchronized. if the mode pin is set to pulse-skipping mode, then the regulator oper - ates in pulse-skipping mode when synchronized. pgood (pin 7/pin 9) : open-drain logic output. pgood is pulled to ground when the voltage on the v fb pin is not within 10% of its set point. freq (pin 8/pin 10): frequency control pin for the in - ternal vco. connecting the pin to gnd forces the vco to a fixed low frequency of 350khz . connecting the pin to intv cc forces the vco to a fixed high frequency of 535khz. other frequencies between 50khz and 900khz can be programmed by using a resistor between freq and gnd. an internal 20a pull-up current develops the voltage to be used by the vco to control the frequency. drvset (pin 9/pin 11) : drv cc regulation program pin. this pin sets the regulated output voltage of the drv cc linear regulator. tying this pin to gnd sets drv cc to 6.0v. tying this pin to intv cc sets drv cc to 10v. other voltages between 5v and 10v can be programmed by placing a resistor (50k to 100k ) between the drvset pin and gnd. an internal 20a pull-up current develops the voltage to be used as the reference to the drv cc ldo. drvuv (pin 10/pin 12) : drv cc uvlo program pin. this pin determines the higher or lower drv cc uvlo and extv cc switchover thresholds, as listed on the electrical characteristics table. connecting drvuv to gnd chooses the lower thresholds whereas tying drvuv to intv cc chooses the higher thresholds. do not float this pin. tg (pin 11/pin 13): high current gate drives for top n- channel mosfet. this is the output of floating high side driver with a voltage swing equal to drv cc superimposed on the switch node voltage sw. sw (pin 12/pin 14): switch node connection to inductor. boost (pin 13/pin 15): bootstrapped supply to the top - side floating driver. a capacitor is connected between the boost and sw pins. v oltage swing at the boost pin is from approximately dr v cc to (v in + drv cc ). bg (pin 14/pin 16): high current gate drive for bottom (synchronous) n-channel mosfet. voltage swing at this pin is from ground to drv cc . drv cc (pin 15/pin 17): output of the internal or external low dropout regulators. the gate drivers are powered from this voltage source. the drv cc voltage is set by the drvset pin. must be decoupled to ground with a minimum of 4.7f ceramic or other low esr capacitor, as close as possible to the ic. do not use the drv cc pin for any other purpose. p in func t ions (qfn/tssop) lt c7801 7801f
10 for more information www.linear.com/ltc7801 ndrv (pin 16/pin 18) : drive output for external pass device of the ndrv ldo linear regulator for drv cc . connect this pin to the gate of an external nmos pass device. an internal charge pump allows ndrv to regulate above v in for low dropout performance. to disable this external ndrv ldo, tie ndrv to drv cc . v in (pin 17/pin 19) : main supply pin. a bypass capacitor should be tied between this pin and the gnd pins. extv cc (pin 18/pin 20): external power input to an internal ldo linear regulator connected to drv cc . this ldo supplies drv cc power from extv cc , bypassing the internal ldo powered from v in or the external ndrv ldo whenever extv cc is higher than its switchover threshold (4.7v or 7.7v depending on the drvuv pin). see drv cc regulators in the applications information section. do not exceed 14v on this pin. do not connect extv cc to a voltage greater than v in . if not used, connect to gnd and place a 330k or smaller resistor between intv cc and ss. run (pin 19/pin 21): run control input. forcing this pin below 1.12v shuts down the controller. forcing this pin below 0.7v shuts down the entire ltc7801, reducing quiescent current to approximately 10a. this pin can be tied to v in for always-on operation. do not float this pin. intv cc (pin 20/pin 22) : output of the internal 5v low dropout regulator. many of the low voltage analog and digital circuits are powered from this voltage source. a low esr 0.1f ceramic bypass capacitor should be con - nected between intv cc and gnd, as close as possible to the ltc7801. ovlo (pin 21/pin 23): overvoltage lockout input. a voltage on this pin above 1.2v disables switching of the controller. the drv cc and intv cc supplies maintain regulation during an ovlo event. exceeding the ovlo threshold triggers a soft-start reset. if the ovlo function is not used, connect this pin to gnd. sense + (pin 22/pin 24): the (+) input to the differential current comparator. the ith pin voltage and controlled offsets between the sense C and sense + pins in conjunc - tion with r sense set the current trip threshold. sense C (pin 23/pin 1) : the (C ) input to the differential current comparator. when sense C is greater than intv cc , the sense C pin supplies power to the current comparator. ss (pin 24/pin 2): soft-start input. the ltc7801 regu - lates the v fb voltage to the smaller of 0.8v or the voltage on the ss pin. an internal 10a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to final regulated output voltage. the ss pin is also used for the regulator shutdown (regsd) feature. a 5a/1a pull-down current can be connected on ss depending on the state of the extv cc ldo and the voltage on ss. see regulator shutdown in the operation section for more information. to defeat the regsd feature, place a 330k or smaller resistor between intv cc and ss. see soft-start pin in the applications information section for more information on defeating regsd. p in func t ions (qfn/tssop) lt c7801 7801f
11 for more information www.linear.com/ltc7801 func t ional diagra m lt c7801 7801f 100k v in 2.0v 1.2v en en en ea? 15m r a r b c c2 c c1 r c c in cb l 20a r sense c out v out c ss 20a pgood ea? 0.88v 0.72v ovlo 10a run 1.2v vco freq pfd pllin drvset v in ndrv drv cc 3v ss ith v fb sense ? sense + gnd bg sw tg boost 5a/1ua sync det charge pump drv cc ldo/uvlo control intv cc extv cc drvuv intv cc 2mv ldo 4.7v/ 7.7v mode cpump_en ndrv ldo v in ldo extv cc ldo 3.5v charge 4r pump dropout detect switch logic drv cc drv cc top bot bot r en topon q s r ea icmp ir sleep 0.88v 7801 bd01 regsd clk shdn 1.8v 0.425v slope comp bclamp 0.80v ss v in
12 for more information www.linear.com/ltc7801 o pera t ion main control loop the ltc7801 uses a constant frequency, current mode step-down architecture. during normal operation, the external top mosfet is turned on when the clock sets the r s latch, and is turned off when the main current comparator, icmp, resets the r s latch. the peak inductor current at which icmp trips and resets the latch is con- trolled by the voltage on the ith pin, which is the output of the error amplifier , ea. the error amplifier compares the output voltage feedback signal at the v fb pin (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage. when the load current increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the ith voltage until the average inductor current matches the new load current. after the top mosfet is turned off each cycle, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. drv cc /extv cc /intv cc power power for the top and bottom mosfet drivers is derived from the drv cc pin. the drv cc supply voltage can be programmed from 5v to 10v by setting the drvset pin. two separate ldos (low dropout linear regulators) can provide power from v in to drv cc . the internal v in ldo uses an internal p-channel pass device between the v in and drv cc pins. to prevent high on-chip power dissipation in high input voltage applications, the ltc7801 also includes an ndrv ldo that utilizes the ndrv pin to supply power to drv cc by driving the gate of an external n-channel mosfet acting as a linear regulator with its source con - nected to drv cc and drain connected to v in . the ndrv ldo includes an internal charge pump that allows ndrv to be driven above v in for low dropout performance. when the extv cc pin is tied to a voltage below its swi - tchover voltage (4.7v or 7.7v depending on the drvuv pin), the v in and ndrv ldos are enabled and one of them supplies power from v in to drv cc . the v in ldo has a slightly lower regulation point than the ndrv ldo. if the ndrv ldo is being used with an external n-channel mosfet, the gate of the mosfet tied to the ndrv pin is driven such that drv cc regulates above the v in ldo regulation point, causing all drv cc current to flow through the external n-channel mosfet, bypassing the internal v in ldo pass device. if the ndrv ldo is not being used, all drv cc current flows through the internal p-channel pass device between the v in and drv cc pins. if extv cc is taken above its switchover voltage, the v in and ndrv ldos are turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies power from extv cc to drv cc . using the extv cc pin allows the drv cc power to be derived from a high efficiency external source such as the ltc7801 switching regulator output. the intv cc supply powers most of the other internal circuits in the ltc7801 . the intv cc ldo regulates to a fixed value of 5v and its power is derived from the drv cc supply. top mosfet driver and charge pump ( cpump_en pin) the top mosfet driver is biased from the floating boot - strap capacitor, c b , which normally recharges during each cycle through an internal switch whenever sw goes low. if the input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top mosfet continuously. the ltc7801 includes an internal charge pump that allows the top mosfet to be turned on continuously at 100% duty cycle. this charge pump deliv - ers current to c b and is enabled when the cpump_en pin is tied to intv cc . tying cpump_en to gnd disables the charge pump and causes the dropout detector to force the top mosfet off for about one twelfth of the clock period every tenth cycle to allow c b to recharge, resulting in an effective 99% max duty cycle. shutdown and start-up (run, ss pins) the ltc7801 can be shut down using the run pin. con - necting the run pin below 1.12v shuts down the main control loop. connecting the run pin below 0.7v disables the controller and most internal circuits, including the drv cc and intv cc ldos. in this state, the ltc7801 draws only 10a of quiescent current. lt c7801 7801f
13 for more information www.linear.com/ltc7801 o pera t ion the run pin has no internal pull-up current, so the pin must be externally pulled up or driven directly by logic. the run pin can tolerate up to 150v (absolute maximum), so it can be conveniently tied to v in in always-on applica- tions where the controller is enabled continuously and never shut down. the start-up of the controller s output voltage v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the 0.8v internal reference, the ltc7801 regulates the v fb voltage to the ss pin voltage instead of the 0.8v reference. this allows the ss pin to be used to program a soft-start by connecting an exter - nal capacitor from the ss pin to gnd. an internal 10a pull-up current charges this capacitor creating a voltage ramp on the ss pin. as the ss voltage rises linearly from 0v to 0.8v (and beyond), the output voltage v out rises smoothly from zero to its final value. light load current operation (burst mode operation, pulse-skipping or forced continuous mode) (mode pin) the ltc7801 can be enabled to enter high efficiency burst mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode at light load currents. to select burst mode operation, tie the mode pin to gnd or a voltage between 0.5v and 1.0v . to select forced continuous operation, tie the mode pin to intv cc . to select pulse-skipping mode, tie the mode pin to a dc voltage greater than 1.4v and less than intv cc C 1.3v. this can be done with a simple resistor divider off intv cc , with both resistors being 100k. when the controller is enabled for burst mode operation, the minimum peak current in the inductor (burst clamp) is adjustable and can be programmed by the voltage on the mode pin. tying the mode pin to gnd sets the default burst clamp to approximately 25% of the maximum sense voltage even when the voltage on the ith pin indicates a lower value. a voltage between 0.5v and 1.0v on the mode pin programs the burst clamp linearly between 10% and 60% of the maximum sense voltage. in burst mode operation, if the average inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith volt - age drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the ith pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the ltc7801 draws to only 40a. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the ith pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (ir) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates discontinuously. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. in forced continuous mode, the output ripple is independent of load current. when the mode pin is connected for pulse-skipping mode, the ltc7801 operates in pwm pulse-skipping mode at light loads. in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator, icmp, may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor cur - rent is not allowed to reverse (discontinuous operation). lt c7801 7801f
14 for more information www.linear.com/ltc7801 this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it pro - vides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. at high output voltages, the efficiency in pulse-skipping mode is comparable to force continuous mode. if the pllin pin is clocked by an external clock sour ce to use the phase-locked loop (see frequency selection and phase-locked loop section), then the ltc7801 operates in forced continuous operation when the mode pin is set to forced continuous or burst mode operation. the controller operates in pulse-skipping mode when clocked by an external clock source with the mode pin set to pulse-skipping mode. frequency selection and phase-locked loop (freq and pllin pins) the selection of switching frequency is a trade-off between efficiency and component size. low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc7801 can be selected using the freq pin. if the pllin pin is not being driven by an external clock source, the freq pin can be tied to gnd, tied to intv cc or programmed through an external resistor. tying freq to gnd selects 350khz while tying freq to intv cc se- lects 535khz . placing a resistor between freq and gnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 12. a phase-locked loop (pll) is available on the ltc7801 to synchronize the internal oscillator to an external clock source that is connected to the pllin pin. the ltc7801s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of the external top mosfet to the rising edge of the synchroniz - ing signal. o pera t ion the vco input voltage is prebiased to the operating fre - quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency , the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clock s to the rising edge of tg. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the ltc7801s phase-locked loop is from approximately 55khz to 1mhz, with a guaran - tee to be between 75khz and 850khz. in other words, the ltc7801 s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. it is recommended that the external clock source swing from ground (0v) to at least 2.8v. input supply overvoltage lockout (ovlo pin) the ltc7801 implements a protection feature that inhibits switching when the input voltage rises above a program - mable operating range. by using a resistor divider from the input supply to ground, the ovlo pin ser ves as a precise input supply voltage monitor. switching is disabled when the ovlo pin rises above 1.2v , which can be configured to limit switching to a specific range of input supply voltage. when switching is disabled, the ltc7801 can safely sus - tain input voltages up to the absolute maximum rating of 150v. input supply overvoltage events trigger a soft-start reset, which results in a graceful recovery from an input supply transient. output overvoltage protection an overvoltage comparator guards against transient over - shoots as well as other more serious conditions that may overvoltage the output. when the v fb pin rises by more than 10% above its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. lt c7801 7801f
15 for more information www.linear.com/ltc7801 o pera t ion power good pin the pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v fb pin voltage is not within 10% of the 0.8v reference voltage. the pgood pin is also pulled low when the run pin is low (shut down). when the v fb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. foldback current when the output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, pro - gressively lowering the peak current limit in proportion to the severity of the overcurrent or short-cir cuit condition. foldback current limiting is disabled during the soft-start interval (as long as the v fb voltage is keeping up with the ss voltage). foldback current limiting is intended to limit power dissipation during overcurrent and short-circuit fault conditions. note that the ltc7801 continuously monitors the inductor current and prevents current runaway under all conditions. regulator shutdown (regsd) high input voltage applications typically require using the extv cc ldo to keep power dissipation low. fault conditions where the extv cc ldo becomes disabled (extv cc below the switchover threshold) for an extended period of time could result in overheating of the ic (or overheating the external n-channel mosfet if the ndrv ldo is used). in the cases where extv cc is tied to the regulator output, this event could happen during overload conditions such as an output short to ground. the ltc7801 includes a regulator shutdown (regsd) feature that shuts down the regulator to substantially reduce power dissipation and the risk of overheating during such events. the regsd circuit monitors the extv cc ldo and the ss pin to determine when to shut down the regulator. refer to the timing diagram in figure 1. whenever ss is above 2.2v and the extv cc ldo is not switched over (the extv cc pin is below the switchover threshold), the internal 10a pull-up current on ss turns off and a 5a pull-down cur - rent turns on, discharging ss. once ss discharges to 2.0v and the ext v cc pin remains below the extv cc switchover threshold, the pull-down current reduces to 1a and the regulator shuts down, eliminating all drv cc switching current. switching stays off until the ss pin discharges to approximately 200mv , at which point the 10a pull-up current turns back on and the regulator re-enables switch - ing. if the short-circuit persists, the regulator cycles on and off at a low duty cycle inter val of about 12%. tg/bg start-up into short-circuit v out /extv cc short removed from v out i ss = 5a (sink) i ss = 10a (source) i ss = 10a (source) i ss = 1a (sink) extv cc switchover threshold (falling) ss 7801 f01 short-circuit event 0v 2.2v 2.0v 0.8v 0.2v 0v figure 1. regulator shutdown operation lt c7801 7801f
16 for more information www.linear.com/ltc7801 the typical application on the first page is a basic ltc7801 application circuit. ltc7801 can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparator. the common mode voltage range on these pins is 0v to 65v (absolute maximum), enabling the ltc7801 to regulate output voltages up to a nominal set point of 60v (allowing margin for tolerances and tran - sients). the sense + pin is high impedance over the full common mode range, drawing at most 1a. this high impedance allows the current comparators to be used in inductor dcr sensing. the impedance of the sense C pin changes depending on the common mode voltage. when sense C is less than intv cc C 0.5v , a small current of less than 1a flows out of the pin. when sense C is above intv cc + 0.5v, a higher current (850a) flows into the pin. between intv cc C 0.5v and intv cc + 0.5v , the current transitions from the smaller current to the higher current. filter components mutual to the sense lines should be placed close to the ltc7801, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 2). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the a pplica t ions i n f or m a t ion programmed current limit unpredictable. if dcr sensing is used (figure 3b), resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. figure 2. sense lines placement with inductor or sense resistor 7801 f02 to sense filter next to the controller inductor or r sense current flow c out low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 3a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the ilim setting. the current comparator threshold voltage sets the peak of the induc - tor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, ? i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 normally in high duty cycle conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion operating at greater than 50% duty factor. the ltc7801 , however, uses a proprietary circuit to nullify the effect of slope compensation on the current limit performance. lt c7801 7801f
17 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc7801 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 3b . the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, power loss through a sense resistor would cost several points of efficiency compared to inductor dcr sensing. (3a) using a resistor to sense current (3b) using the inductor dcr to sense current figure 3. current sensing methods 7801 f03a ltc7801 boost tg sw bg gnd sense ? sense + v in v out r sense cap placed near sense pins 7801 f03b ltc7801 v in v out c1* r2 *place c1 near sense pins r sense(eq) = dcr(r2/(r1+r2)) l dcr inductor r1 (r1||r2) ? c1 = l/dcr boost tg sw bg gnd sense ? sense + if the external (r1||r2) t c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is : r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for v sense(max) in the electrical charac - teristics table. next, determine the dcr of the inductor . when provided, use the manufacturer s maximum value, usually given at 20c. increase this value to account for the temperature coefficient of copper resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value (r d ), use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current. the equivalent resistance r1||r2 is scaled to the tempera - ture inductance and maximum dcr: r1|| r2 = l (dcr at 20c) t c1 lt c7801 7801f
18 for more information www.linear.com/ltc7801 the values for r1 and r2 are: r1 = r1|| r2 r d ; r2 = r1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1 . however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor v alue calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet switching and gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current, ? i l , decreases with higher induc - tance or higher frequency and increases with higher v in : ? i l = 1 (f)(l) v out 1 ? v out v in ? ? ? ? ? ? a pplica t ions i n f or m a t ion accepting larger values of ? i l allows the use of low in - ductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ? i l = 0.3(i max ). the maximum ? i l occurs at the maximum input voltage. the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below the burst clamp, which can be programmed between 10% and 60% of the current limit determined by r sense . (for more information see the burst clamp programming sec - tion.) lower inductor values (higher ? i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet selection t wo external power mosfet s must be selected for the ltc7801 controller: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. lt c7801 7801f
19 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion the peak-to-peak drive levels are set by the drv cc volt- age. this voltage can range from 5v to 10v depending on c o nfiguration of the drvset pin. therefore, both logic-level and standard-level threshold mosfets can be used in most applications depending on the programmed drv cc voltage. pay close attention to the bv dss specification for the mosfets as well. the ltc7801 s ability to adjust the gate drive level between 5v to 10v (opti-drive) allows an application circuit to be precisely optimized for efficiency. when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input cur - rent decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency . selection criteria for the power mosfet s include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: m ain switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i out(max) ( ) 2 1 + ( ) r ds(on) + (v in ) 2 i out(max) 2 ? ? ? ? ? ? (r dr )(c miller ) ? 1 v drvcc ? v thmin + 1 v thmin ? ? ? ? ? ? (f) p sync = v in ? v out v in i out(max) ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) and r dr (approximately 2 ) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the main n-channel equations include an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. c in and c out selection the selection of c in is usually based off the worst-case rms input current. the highest (v out )(i out ) product needs to be used in the formula shown in equation 1 to determine the maximum rms capacitor current requirement. lt c7801 7801f
20 for more information www.linear.com/ltc7801 in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c in required i rms i max v in (v out )(v in ? v out ) [ ] 1/2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc7801, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the ltc7801, is also suggested. a small (10) resistor placed between c in (c1) and the v in pin provides further isolation. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( ? v out ) is approximated by: ? v out ? i l esr + 1 8 ? f ? c out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and ? i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. a pplica t ions i n f or m a t ion setting output voltage the ltc7801 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in figure 4. the regulated output voltage is determined by : v out = 0.8v 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feedforward ca - pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. 7801 f04 ltc7801 v fb r b c ff r a v out figure 4. setting output voltage run pin and overvoltage/undervoltage lockout the ltc7801 is enabled using the run pin. it has a rising threshold of 1.2v with 80mv of hysteresis. pulling the run pin below 1.12v shuts down the main control loop. pull - ing it below 0.7v disables the controller and most internal cir cuits, including the dr v cc and intv cc ldos. in this state the ltc7801 draws only 10a of quiescent current. the run pin is high impedance below 3v and must be externally pulled up/down or driven directly by logic. the run pin can tolerate up to 150v (absolute maximum), so it can be conveniently tied to v in in always-on applications where the controller is enabled continuously and never shut down. above 3v, the run pin has approximately a 15m impedance to an internal 3v clamp. lt c7801 7801f
21 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion figure 5. adjustable uv and ov lockout the run and ovlo pins can alternatively be configured as undervoltage (uvlo) and overvoltage (ovlo) lockouts on the v in supply with a resistor divider from v in to ground. a simple resistor divider can be used as shown in figure 5 to meet specific v in voltage requirements. run 7801 f05 r3 v in ltc7801 r4 r5 ovlo for applications that do not require a precise ovlo, the ovlo pin can be tied directly to ground. the run pin in this type of application can be used as an external uvlo using the previous equations with r5 = 0. similarly, for applications that do not require a precise uvlo, the run pin can be tied to v in . in this configura - tion, the uvlo threshold is limited to the internal drv cc uvlo thresholds as shown in the electrical characteristics table. the resistor values for the ovlo can be computed using the previous equations with r3 = 0. soft-start (ss) pin the start-up of v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the internal 0.8v reference, the ltc7801 regulates the v fb pin voltage to the voltage on the ss pin instead of the internal reference. the ss pin can be used to program an external soft-start function. soft-start is enabled by simply connecting a capacitor from the ss pin to ground, as shown in figure 6. an internal 10a current source charges the capacitor, providing a linear ramping voltage at the ss pin. the ltc7801 will regulate its feedback voltage (and hence v out ) according to the voltage on the ss pin, allowing v out to rise smoothly from 0v to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 0.8v 10a the current that flows through the r3-r4-r5 divider will directly add to the shutdown, sleep, and active current of the ltc7801 , and care should be taken to minimize the impact of this current on the overall efficiency of the ap - plication circuit. resistor values in the megaohm range may be required to keep the impact on quiescent shutdown and sleep currents low . to pick resistor values, the sum total of r3 + r3+ r5 (r total ) should be chosen first based on the allowable dc current that can be drawn from v in . the individual values of r3, r4 and r5 can be calculated from the following equations: r5 = r total ? 1.20v rising v in ovlo threshold r4 = r total ? 1.20v rising v in ovlo threshold ? r5 r3 = r total ? r5 ? r4 figure 6. using the ss pin to program soft-start 7801 f06 ltc7801 ss gnd c ss lt c7801 7801f
22 for more information www.linear.com/ltc7801 the ss pin also controls the timing of the regulator shutdown (regsd) feature (as discussed in regulator shutdown of the operation section). if the application does not require the use of the extv cc ldo (the extv cc pin is grounded), the regsd feature must be defeated with a pull-up resistor between ss and intv cc , as shown in figure 7. any resistor 330k or smaller between ss and intv cc defeats the 5a pull-down current on ss that turns on once ss reaches 2.2v (with the extv cc ldo not enabled), preventing ss from discharging to 2.0v and shutting down the regulator. note the current through this pull-up resistor adds to the internal 10a ss pull-up current at start-up, causing the total soft-start time to be shorter than what it is calculated without the pull-up resistor. the total soft-start time with the pull-up resistor is approximately: t ss c ss ? 0.8v 10a + 4.6v r ss ? ? ? ? ? ? where r ss is the value of the resistor between the ss and intv cc pins. a pplica t ions i n f or m a t ion figure 7. using the ss pin to program soft-start with extv cc unused/grounded to defeat regsd 7801 f07 ltc7801 ss gnd intv cc extv cc c ss r ss uses an internal p-channel pass device between the extv cc and drv cc pins. the ndrv ldo utilizes the ndrv pin to drive the gate of an external n-channel mosfet acting as a linear regulator with its drain connected to v in . the ndrv ldo provides an alternative method to supply power to drv cc from the input supply without dissipating the power inside the ltc7801 ic. it has an internal charge pump that allows ndrv to be driven above the v in sup- ply, allowing for low dropout performance. the v in ldo has a slightly lower regulation point than the ndrv ldo, such that all drv cc current flows through the external n- channel mosfet (and not through the internal p-channel pass device) once drv cc reaches regulation. when laying out the pc board, care should be taken to route ndrv away from any switching nodes, especially sw, tg, and boost. coupling to the ndrv node could cause its voltage to collapse and the ndrv ldo to lose regulation. if this occurs, the internal v in ldo would take over and maintain drv cc voltage at a slightly lower regulation point. however, internal heating of the ic would become a concern. high frequency noise on the drain of the external nfet could also couple into the ndrv node (through the gate-to-drain capacitance of the ndrv nfet) and adversely affect ndrv regulation. the following are methods that could mitigate this potential issue (refer to figure 8a). 1. add local decoupling capacitors right next to the drain of the external ndrv nfet in the pcb layout. 2. insert a resistor ( ~100 ) in series with the gate of the ndrv nfet. 3. insert a small capacitor ( ~1nf ) between the gate and source of the ndrv nfet. when testing the application circuit, be sure the ndrv voltage does not collapse over the entire input voltage and output current operating range of the buck regulator. drv cc regulators (opti-drive) the ltc7801 features three separate low dropout linear regulators (ldo) that can supply power at the drv cc pin. the internal v in ldo uses an internal p-channel pass device between the v in and drv cc pins. the internal extv cc ldo lt c7801 7801f
23 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion 7801 f08a ltc7801 c2* c1* r1* *r1, c1 and c2 are optional v in v in drv cc gnd ndrv 7801 f08b ltc7801 v in v in drv cc gnd ndrv figure 8a. configuring the ndrv ldo figure 8b. disabling the ndrv ldo if the ndrv ldo is not being used, connect the ndrv pin to drv cc (figure 8b). the drv cc supply is regulated between 5v to 10v, de - pending on how the drvset pin is set. the internal v in and extv cc ldos can supply a peak current of at least 50ma . the drv cc pin must be bypassed to ground with a minimum of 4.7f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. the drvset pin programs the drv cc supply voltage and the drvuv pin selects different drv cc uvlo and extv cc switchover threshold voltages. table 1a summarizes the different drvset pin configurations along with the volt - age settings that go with each configuration. table 1b summarizes the different drvuv pin settings. t ying the drvset pin to intv cc programs drv cc to 10v . tying the drvset pin to gnd programs drv cc to 6v. placing a 50k to 100k resistor between drvset and gnd the programs drv cc between 5v to 10v, as shown in figure 9. table 1a. drvset pin drv cc voltage gnd 6v intv cc 10v resistor to gnd 50k to 100k 5v to 10v table 1b. drvuv drv cc uvlo rising/falling thresholds extv cc switchover rising/falling threshold gnd 4.0v/3.8v 4.7v/4.45v intv cc 7.5v/6.7v 7.7v/7.45v figure 9. relationship between drv cc voltage and resistor value at drvset pin high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc7801 to be exceeded. the dr v cc current, which is dominated by the gate charge current, may be supplied by the v in ldo, ndrv ldo or the extv cc ldo. when the voltage on the extv cc pin is less than its switchover threshold (4.7v or 7.7v as determined by the drvuv pin described above), the v in and ndrv ldos are enabled. power dissipation in this case is highest and is equal to v in ? idrv cc . if the ndrv ldo is not being used, this power is dissipated inside the ic. the gate charge current is dependent on operating frequency as discussed in the efficiency con - siderations section. lt c7801 7801f 70 75 80 85 90 95 100 105 4.5 5.0 ndrv ldo 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 or extv cc ldo 10.5 drv cc voltage (v) 7801 f09 internal v in ldo drvset pin resistor (k) 50 55 60 65
24 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, if drv cc is set to 6v , the drv cc current is limited to less than 32ma from a 40v supply when not using the extv cc or ndrv ldos at a 70c ambient tem - perature in the qfn package: t j = 70c + (32ma)(40v)(43c/w) = 125c to prevent the maximum junction temperature from being exceeded, the v in supply current must be checked while operating in forced continuous mode (mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above its swi - tchover threshold, the v in and ndrv ldos are turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above the switchover threshold minus the comparator hysteresis. the extv cc ldo attempts to regulate the drv cc voltage to the voltage as programmed by the drvset pin, so while extv cc is less than this voltage, the ldo is in dropout and the drv cc voltage is approximately equal to extv cc . when extv cc is greater than the programmed voltage, up to an absolute maximum of 14v , drv cc is regulated to the programmed voltage. using the extv cc ldo allows the mosfet driver and control power to be derived from the ltc7801s switch - ing regulator output ( 4.7v/7.7v v out 14v ) during normal operation and from the v in or ndrv ldo when the output is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc ldo than is specified, an external schottky diode can be added between the extv cc and drv cc pins. in this case, do not apply more than 10v to the extv cc pin and make sure that extv cc v in . significant efficiency and thermal gains can be realized by powering drv cc from the output, since the v in cur - rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). for 5v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to an 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (32ma)(8.5v)(43c/w) = 82c however, for 3.3v and other low voltage outputs, addi - tional circuitry is required to derive drv cc power from the output. the following list summarizes the five possible connec - tions for extv cc : 1. ext v cc grounded. this will cause drv cc to be pow - ered from the internal v in or ndrv ldo resulting in an efficiency penalty of up to 10% at high input volt- ages. if extv cc is grounded, the regsd feature must be defeated with a pull-up resistor 330k or smaller between ss and intv cc . 2. ext v cc connected directly to the regulator output. this is the normal connection for a 5v to 14v regulator and provides the highest efficiency. 3. ext v cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc v in . 4. ext v cc connected to the regulator output through an external zener diode. if the output voltage is greater than 14v , a zener diode can be used to drop the necessary voltage between v out and extv cc such that extv cc remains below 14v (figure 10). in this configuration, a bypass capacitor on extv cc of at least 0.1f is recommended. an optional resistor between extv cc and gnd can be inserted to ensure adequate bias current through the zener diode. 7801 f10 ltc7801 v out > 14v extv cc gnd extv cc < 14v 0.1f figure 10. using a zener diode between v out and extv cc lt c7801 7801f
25 for more information www.linear.com/ltc7801 5. ext v cc connected to an output-derived boost network off the regulator output. for 3.3v and other low volt - age regulators, efficiency gains can still be realized by connecting ext v cc to an output-derived voltage that has been boosted to greater than 4.7v/7.7v. ensure that extv cc v in . intv cc regulator an additional p-channel ldo supplies power at the intv cc pin from the drv cc pin. whereas drv cc powers the gate drivers, intv cc powers much of the ltc7801s internal circuitry. the intv cc supply must be bypassed with a 0.1f ceramic capacitor. intv cc is also used as a pull-up to bias other pins, such as mode, pgood, etc. topside mosfet driver supply (c b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. the ltc7801 features an internal switch between drv cc and the boost pin. this internal switch eliminates the need for an external bootstrap diode between drv cc and boost. capacitor c b in the functional diagram is charged through this internal switch from drv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate-source of the mosfet. this enhances the top mosfet switch and turns it on. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v drvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). burst clamp programming burst mode operation is enabled if the voltage on the mode pin is 0v or in the range between 0.5v to 1v. the burst clamp, which sets the minimum peak inductor cur - rent, can be programmed by the mode pin voltage. if the mode pin is grounded, the burst clamp is set to 25% of the maximum sense voltage (v sense(max) ). a mode pin voltage between 0.5v and 1v varies the burst clamp linearly between 10% and 60% of v sense(max) through the following equation: a pplica t ions i n f or m a t ion burst clamp = v mode ? 0.4v 1v ? 100 where v mode is the voltage on the mode pin and burst clamp is the percentage of v sense(max) . the burst clamp level is determined by the desired amount of output voltage ripple at low output loads. as the burst clamp increases, the sleep time between pulses and the output voltage ripple increase. the mode pin is high impedance and v mode can be set by a resistor divider from the intv cc pin (figure 11a). alternatively, the mode pin can be tied directly to the v fb pin to set the burst clamp to 40% (v mode = 0.8v), or through an additional divider resistor ( r3 ). as shown in figure 11b , this resistor can be placed below v fb to program the burst clamp between 10% and 40% (v mode = 0.5v to 0.8v) or above v fb to program the burst clamp between 40% and 60% (v mode = 0.8v to 1.0v). burst clamp = 10% to 60% 7801 f11a ltc7801 r2 r1 intv cc mode (11a) using intv cc to program the burst clamp burst clamp = 10% to 40% v out ltc7801 r3 r1 v fb mode r2 burst clamp = 40% to 60% v out 7801 f11b ltc7801 r2 r1 v fb mode r3 (11b) using v fb to program the burst clamp figure 11. programming the burst clamp lt c7801 7801f
26 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion fault conditions: current limit and current foldback the ltc7801 includes current foldback to help limit load current when the output is shorted to ground. if the output voltage falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 40% of its maximum selected value. under short-circuit conditions with very low duty cycles, the ltc7801 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time, t on(min) , of the ltc7801 (80ns), the input voltage and inductor value: ? i l(sc) = t on(min) v in l ? ? ? ? ? ? the resulting average short-circuit current is: i sc = 45% ? i lim(max) ? 1 2 ? i l(sc) fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the control - ler is operating. a comparator monitors the output for overvoltage condi - tions. the comparator detects faults greater than 10% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the over voltage condition is cleared. the bottom mosfet remains on continuously for as long as the over voltage condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. fault conditions: overtemperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on chip, the overtemperature shutdown circuitry will shut down the ltc7801 . when the junction temperature exceeds ap - proximately 175 c , the overtemperature circuitry disables the drv cc ldo, causing the drv cc supply to collapse and effectively shutting down the entire ltc7801 chip. once the junction temperature drops back to the approximately 155c , the drv cc ldo turns back on. long term over - stress (t j > 125c ) should be avoided as it can degrade the performance or shorten the life of the part. phase-locked loop and frequency synchronization the ltc7801 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (vco). this allows the turn-on of the top mosfet to be locked to the rising edge of an external clock signal applied to the pllin pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the inter - nal oscillator s frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. lt c7801 7801f
27 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, c lp , holds the voltage at the vco input. note that the ltc7801 can only be synchronized to an external clock whose frequency is within range of the ltc7801 s internal vco, which is nominally 55khz to 1mhz. this is guaranteed to be between 75khz and 850khz. the ltc7801 is guaranteed to synchronize to an external clock that swings up to at least 2.8v and down to 0.5v or less. rapid phase-locking can be achieved by using the freq pin to set a free-running frequency near the desired synchronization frequency. the vco s input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchronization. although it is not required that the free- running frequency be near the external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. table 2 summarizes the different states in which the freq pin can be used. when synchronized to an external clock, the ltc7801 operates in forced continuous mode at light loads if the mode pin is set to burst mode operation or forced continuous operation. if the mode pin is set to pulse-skipping operation, the ltc7801 maintains pulse- skipping operation when synchronized. table 2. freq pin pllin pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor to gnd dc voltage 50khz to 900khz any of the above external clock 75khz to 850khz phase locked to external clock minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the ltc7801 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in (f) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc7801 is approximately 80ns . however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns . this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 7801 f12 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 figure 12. relationship between oscillator frequency and resistor value at the freq pin lt c7801 7801f
28 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a per cent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc7801 circuits: 1) ic v in current, 2) drv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mos - fet driver and control currents. v in current typically results in a small (< 0.1%) loss. 2. dr v cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from drv cc to ground. the resulting dq/dt is a current out of drv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. sup plying drv cc from an output-derived source power through extv cc will scale the v in current re - quired for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20v to 5v application, 10ma of drv cc current results in approximately 2.5ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis - tor and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resis - tance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m , r l = 50m, r sense = 10m and r esr = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the top mosfet(s) and become significant only when operating at high input voltages (typically 20v or greater). transition losses can be estimated from: transition loss = (1.7) ? v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has ad - equate charge storage and very low esr at the switching frequenc y . a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including schottky conduc - tion losses during dead-time and inductor core losses generally account for less than 2% total additional loss. lt c7801 7801f
29 for more information www.linear.com/ltc7801 checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti- loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in the first page circuit will provide an adequate starting point for most applications. the ith series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms a pplica t ions i n f or m a t ion that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca - pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de - creasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. lt c7801 7801f
30 for more information www.linear.com/ltc7801 a pplica t ions i n f or m a t ion design example as a design example, assume v in = 12v (nominal), v in = 22v (max), v out = 3.3v , i max = 5a , v sense(max) = 75mv and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. tie the freq pin to gnd, generating 350khz operation. the inductor ripple current can be calculated from the following equation: ? i l = v out (f)(l) 1 ? v out v in(nom) ? ? ? ? ? ? ? ? a 4.7h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.73a. increasing the ripple current will also help ensure that the minimum on-time of 80ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) (f) = 3.3v 22v(350khz) = 429ns the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (66mv): ? r sense 66mv 5.73a ? 0.01 ? choosing 1% resistors: r a = 24.9k and r b = 78.7k yields an output voltage of 3.33v. the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fd s6982s dual mosfet results in: r ds(on) = 0.035/0.022 , c miller = 215pf . with 6v gate drive and maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v (5a) 2 1 + (0.005)(50 c ? 25 c [ ] (0.035 ? ) + (22v) 2 5a 2 (2.5 ? )(215pf) ? 1 6v ? 2.3v + 1 2.3v ? ? ? ? ? ? (350khz) = 308mw a short-circuit to ground will result in a folded back cur - rent of: i sc = 34mv 0.01 ? ? 1 2 80ns(22v) 4.7h ? ? ? ? ? ? = 3.21a with a typical value of r ds(on) and = (0.005/c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = (3.21a) 2 (1.125) (0.022) = 255mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.02 (1.45a) = 29mv p-p pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. 1. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c drvcc must return to the combined c out (C ) terminals. the path formed by the top n-channel mosfet, bottom n-channel mosfet and the c in ca- pacitor should have short leads and pc trace lengths. t h e output capacitor ( C ) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other. 2. does the ltc7801 v fb pins resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. lt c7801 7801f
31 for more information www.linear.com/ltc7801 4. is the drv cc and decoupling capacitor connected close to the ic, between the drv cc and the ground pin? this capacitor carries the mosfet drivers current peaks. 5. keep the sw, tg, and boost nodes away from sensi - tive small-signal nodes. all of these nodes have ver y large and fast moving signals and therefore should be kept on the output side of the ltc7801 and occupy minimum pc trace area. 6. use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the drv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. pc board layout debugging it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be main - tained over the input voltage range down to dropout and until the output load drops below the low current opera - tion thresholdtypically 25% of the maximum designed current level in burst mode operation. t h e duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. over compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the output to verify operation. a pplica t ions i n f or m a t ion investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost , sw , tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , the top mosfet and the bottom mosfet to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordon t worry, the regulator will still maintain control of the output voltage. pin clearance/creepage considerations the ltc7801 is available in two packages (qfn and tssop) with identical functionality. however, the space between adjacent pins on the ltc7801 may not provide sufficient pc board trace clearance between high and low voltage pins in some higher voltage applications. in applications where clearance is required, the ltc3895 should be used. the ltc3895 has removed pins between all the adjacent high voltage and low voltage pins, providing 0.68mm clearance which is sufficient for most applications. for more information, refer to the printed circuit board design standards described in ipc-2221 (www.ipc.org). lt c7801 7801f
32 for more information www.linear.com/ltc7801 typical a pplica t ions high efficiency 140v to 3.3v step-down regulator efficiency and power loss vs load current efficiency vs load current efficiency vs input voltage lt c7801 7801f 0.1f in = 24v v out = 3.3v pulse?skipping efficiency ps loss fcm loss fcm l1 efficiency burst loss load current (a) 0.0001 0.001 0.01 0.1 1 10 0 3.3h 10 20 30 40 50 60 70 80 90 100 c sns 1 10 100 1k 10k 100k efficiency (%) power loss (mw) 7801 ta02b v out = 3.3v 1nf v in = 12v v in = 24v v in = 48v v in = 100v v in = 140v load current (a) 0.0001 0.001 0.01 0.1 c itha 1 10 0 10 20 30 40 50 60 70 6.8nf 80 90 100 efficiency (%) 7801 ta02c v out = 3.3v m bot : bsc190n15ns3g, i load = 5a m bot : bsc190n15ns3g, i load = 10a m bot : bsc520n15ns3g, i load = 5a m bot : bsc520n15ns3g, i load = 10a c ithb input voltage (v) 0 20 40 60 80 100 120 140 50 100pf 55 60 65 70 75 80 85 90 efficiency (%) 7801 ta02d c ss 470f 0.1f c intv cc 0.1f r pgood 100k c drv cc 4.7f 100f c ina 0.47f c outa c inb r ith 4.99k r freq 34k r b 267k r a 196k l2 100f 470h 7801 ta02a 4.7f c out2 0.47f c inc v in intv cc cpump_en drvset c outb drvuv ith ss ltc7801 tg sw bg sense + sense ? extv cc r sense v fb boost ndrv drv cc v in 12v to 140v v out 3.3v 10a pgood 3m ovlo pllin gnd run freq m top , m bot : bsc520n15ns3g l1: wurth 7443310330 c outa : kemet t520d477m0o6a1e015 l2: coilcraft mss1048t-474klb m top m bot x2 x3 mode v in ltc3639 run ovlo i set fbo gnd c b gnd gnd sw v fb vprg1 vprg2 ss x2 burst efficiency v
33 for more information www.linear.com/ltc7801 typical a pplica t ions high efficiency switching surge stopper 100s/div gnd v in 20v/div v out 20v/div 7801 ta03b 20ms/div gnd v in 20v/div v out 20v/div 7801 ta03c lt c7801 7801f c b 0.1f l1 15h c sns 1nf c itha 4.7nf c ithb 100pf 39f c ss 0.1f c intv cc 0.1f c drv cc 4.7f 100f c ina 0.47f c inb c outa r ith 10k r freq 42.2k r ovlob 1m r ovloa 34.9k r ss 100k 22f c ovlo 3.3f r a 46.4k r b 1m r ovloc 1m v in intv cc c outb cpump_en drvset drvuv ith ss 7801 ta03a ltc7801 tg sw bg r sense sense+ sense- extv cc v fb boost ndrv drv cc v in 12v* v out 8m 12v** 5a ovlo gnd run freq pllin m top : bsc190n15ns3g m bot : bsc520n15ns3g l1: wurth 74435571500 m bot c outa : os-con 35svpf39m x4 mode pin not used in this circuit: pgood **v out follows v in when v in < 18v, v out regulates to 18v when v in > 18v *surges to 140v, ovlo timer limits switching time above 36v to 4 seconds m top
34 for more information www.linear.com/ltc7801 typical a pplica t ions high efficiency 140v to 24v step-down regulator 7801 ta04 lt c7801 7801f l1 33h c sns 1nf c itha 3.3nf c ithb 100pf c ss 0.1f 68f c intv cc 0.1f c drv cc 4.7f 100f c ina 0.47f c inb r ith 23.7k c outa r a 28k r b 806k d ext 12v r sense 6m r freq 36.5k 10f c ext 1f v in intv cc cpump_en drvset drvuv ith ss ltc7801 c outb tg sw bg sense + sense ? v fb boost ndrv drv cc v in mbot 8v to 140v v out 24v* 5a ovlo gnd run freq pllin mtop, mbot: bsc520n15ns3g mtop d ext : diodes inc. smaz12-13-f l1: wurth 7443633300 c outa : suncon 35ce68lx x4 mode pin not used in this circuit: pgood *v out follows v in when x2 v in < 24v v 10 out c b extv cc 0.1f
35 for more information www.linear.com/ltc7801 high efficiency 60v to 5v step-down regulator with surge protection to 140v typical a pplica t ions 7801 ta05 lt c7801 7801f c itha 3.3nf c ithb 100pf c ss 0.1f c intv cc 0.1f c drv cc 4.7f 470f 100f c ina 0.47f c inb r ith 4.99k 1m 191k r freq 36.5k c outa r ovlob 1m r ovloa 18.7k r ss 330k r sns 2.43k l1 4.7h mbot v in intv cc cpump_en pllin drvset drvuv ith ss ltc7801 tg mtop sw bg sense + sense ? extv cc v fb boost ndrv drv cc v in c b 8v to 60v* v out 5v 10a ovlo gnd run freq mtop: bsc520n15ns3g mbot: bsc042ne7ns3g 0.1f l1: coilcraft xal1010-472me c outa : kemet t520d477m006ate015 x3 pins not used in this circuit: pgood *surges to 140v, ovlo stops switching when v in > 65v x2 100f c outb c sns x2 mode 470nf
36 for more information www.linear.com/ltc7801 p ackage descrip t ion please refer to http://www.linear.com/product/ltc7801#packaging for the most recent package drawings. 4.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 23 24 1 2 bottom view?exposed pad 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd24) qfn 0506 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.65 0.05 2.00 ref 3.00 ref 4.10 0.05 5.50 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 2.00 ref 3.00 ref 3.65 0.10 3.65 0.05 ufd package 24-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1696 rev a) lt c7801 7801f
37 for more information www.linear.com/ltc7801 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/product/ltc7801#packaging for the most recent package drawings. fe24 (aa) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 7.70 ? 7.90* (.303 ? .311) 3.25 (.128) 2.74 (.108) 2021222324 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.25 (.128) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1771 rev b) exposed pad variation aa lt c7801 7801f
38 for more information www.linear.com/ltc7801 lt 0517 ? printed in usa www.linear.com/ltc7801 ? linear technology corporation 2017 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3895 150v low i q , synchronous step-down dc/dc controller 100% duty cycle capability, adjustable 5v to 10v gate drive 4v v in 140v, 150v pk , 0.8v v out 60v, i q = 40a pll fixed frequency 50khz to 900khz ltc7800 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle 4v v in 60v, 0.8v v out 24v, i q = 50a pll fixed frequency 320khz to 2.25mhz ltc3871 bidirectional polyphase ? synchronous buck or boost controller v high up to 100v, v low up to 30v, high power buck or boost on demand ltc3892/ ltc3892-1 60v low i q , dual, 2-phase synchronous step-down dc/dc controller with 99% duty cycle 4v v in 60v, 0.8v v out 0.99v in , pll fixed frequency 50khz to 900khz, adjustable 5v to 10v gate drive, i q = 29a ltc3639 high efficiency, 140v 100ma synchronous step-down regulator integrated power mosfets, 4v v in 150v, 0.8v v out v in , i q = 12a, msop-16 (12) ltc3638 high efficiency, 150v 250ma synchronous step-down regulator integrated power mosfets, 4v v in 150v, 0.8v v out v in , i q = 12a, msop-16 (12) ltc7138 high efficiency, 150v 400ma synchronous step-down regulator integrated power mosfets, 4v v in 150v, 0.8v v out v in , i q = 12a, msop-16 (12) ltc3899 60v triple output, buck/buck/boost synchronous controller with 30a burst mode i q 4.5v(down to 2.2v after start-up) v in 60v, buck v out range: 0.8v to 60v, boost v out up to 60v ltc7860 high efficiency switching surge stopper 3.5v v in 60v, expandable to 200v + , adjustable v out clamp and current limit, power inductor improves emi, msop-12 lt8631 100v, 1a synchronous micropower step-down regulator integrated power mosfets, 3v v in 100v, 0.8v v out 60v, i q = 7a, tssop-20(16) ltc3896 150v low i q , synchronous inverting dc/dc controller 4v v in 140v, 150v pk , C60v v out C0.8v, ground-reference interface pins, adjustable 5v to 10v gate drive, i q = 40a LTC3897 polyphase synchronous boost controller with input/output protection and adjustable gate drive voltage 4.5v v in 65v, v out up to 60v, i q = 55a fixed frequency 50khz to 900khz ltc7103 105v, 2.3a low emi synchronous step-down regulator 4.4v v in 105v, 1v v out v in , i q = 2a fixed frequency 200khz to 2mhz, 5mm 6mm qfn figure 13. high efficiency 140v to 12v step-down regulator lt c7801 7801f c b 0.1f l1 33h c sns 1nf c itha 4.7nf c ithb 100pf 150f r a 36.5k c ss 0.1f c intv cc 0.1f r pgood 100k c drv cc 4.7f c outa 100f c ina 0.47f c inb r b 511k r ith 10k r freq 30.1k 22f r drvset 80.6k c b 10pf v in intv cc cpump_en drvset drvuv ith c outb ss ltc7801 tg sw bg sense + sense ? extv cc v fb boost r sense ndrv drv cc v in 7v to 140v v out 12v* 5a *v out follows v in when v in < 12v ovlo pgood 8m gnd run freq 7801 f13 pllin m top , m bot : bsc520n15ns3g l1: wurth 7443633300 c outa : avx tpsd157m016r0125 x2 x3 m bot mode x3 m top

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